Hardware Reference
In-Depth Information
65
i <= 0;
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j <= 0;
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elsif falling_edge(spi_clk) then
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if pr_state /= nx_state then
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i <= 0;
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j <= 0;
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elsif not (i=imax and j=jmax) then
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if i/=imax then
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i <= i + 1;
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elsif j/=jmax then
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i <= 0;
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j <= j + 1;
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end if;
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end if;
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end if;
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end process;
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--FSM state register:
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process (spi_clk, rst)
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begin
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if (rst='1') THEN
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pr_state <= idle;
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elsif falling_edge(spi_clk) then
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pr_state <= nx_state;
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end if;
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end process;
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--FSM combinational logic:
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process (all)
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begin
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--Default values:
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SSn <= '0';
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SCK <= spi_clk;
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MOSI <= '-';
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imax <= 0;
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jmax <= 0;
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--Other values:
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case pr_state IS
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when idle =>
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SSn <= '1';
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SCK <= '0';
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if wr='1' then
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nx_state <= WREN;
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elsif rd='1' then
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nx_state <= READx;
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else
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nx_state <= idle;
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end if;
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--Data-write sequence:
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when WREN =>
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MOSI <= WREN_opcode(7-i);
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imax <= 7;
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if i=imax then
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nx_state <= deselect;
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else
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nx_state <= WREN;
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end if;
