Additional Design Examples - Finite State Machines in Hardware - page 303

133 SDA <= '0';

134 nx_state <= hold;

135 when hold =>

136 SCL <= '1';

137 SDA <= '1';

138 if wr='0' then

139 nx_state <= idle;

140 else

141 nx_state <= hold;

142 end if;

143 --Data-write states:

144 when initial_addr_wr =>

145 SDA <= initial_addr_for_wr(8-i);

146 i <= i_reg + 1;

147 if i=8 then

148 nx_state <= ack2;

149 else

150 nx_state <= initial_addr_wr;

151 end if;

152 when ack2 =>

153 SDA <= 'Z';

154 nx_state <= wr_data;

155 when wr_data =>

156 SDA <= data_out(j)(8-i);

157 i <= i_reg + 1;

158 j <= j_reg;

159 if i=8 then

160 nx_state <= ack3;

161 else

162 nx_state <= wr_data;

163 end if;

164 when ack3 =>

165 SDA <= 'Z';

166 j <= j_reg + 1;

167 if j<7 then

168 nx_state <= wr_data;

169 else

170 nx_state <= stop;

171 end if;

172 --Data-read states:

173 when initial_addr_rd =>

174 SDA <= initial_addr_for_rd(8-i);

175 i <= i_reg + 1;

176 if i=8 then

177 nx_state <= ack4;

178 else

179 nx_state <= initial_addr_rd;

180 end if;

181 when ack4 =>

182 SDA <= 'Z';

183 nx_state <= restartL;

184 when restartL =>

185 SCL <= '0';

186 SDA <= '1';

187 nx_state <= restartR;

188 when restartR =>

189 SCL <= '1';