Hardware Reference
In-Depth Information
76
i2c_clk <= not i2c_clk;
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count := 0;
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end if;
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end if;
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end process;
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--FSM state register + Auxiliary register:
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process (i2c_clk, rst)
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begin
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if rst='1' then
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pr_state <= idle;
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i_reg <= 0;
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j_reg <= 0;
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elsif falling_edge(i2c_clk) then
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pr_state <= nx_state;
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i_reg <= i;
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j_reg <= j;
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end if;
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end process;
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--FSM combinational logic:
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process (all)
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begin
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--Default values:
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SCL <= i2c_clk;
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i <= 0;
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j <= 0;
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case pr_state IS
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--Common states:
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when idle =>
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SCL <= '1';
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SDA <= '1';
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if wr='1' or rd='1' then
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nx_state <= start;
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else
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nx_state <= idle;
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end if;
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when start =>
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SCL <= '1';
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SDA <= '0';
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nx_state <= slave_addr_wr;
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when slave_addr_wr =>
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SDA <= slave_addr_for_wr(8-i);
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i <= i_reg + 1;
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if i=8 then
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nx_state <= ack1;
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else
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nx_state <= slave_addr_wr;
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end if;
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when ack1 =>
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SDA <= 'Z';
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if wr='1' then
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nx_state <= initial_addr_wr;
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else
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nx_state <= initial_addr_rd;
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end if;
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when stop =>
