Hardware Reference
In-Depth Information
21
signal outp, outp_reg: std_logic_vector(...);
22
23 begin
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--Timer:
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(same as for category 2 Moore, section 9.2)
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--Auxiliary register:
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process (clk, rst)
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begin
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if (rst='1') then
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outp_reg <= <initial value>;
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elsif rising_edge(clk) then
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outp_reg <= outp;
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end if;
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end process;
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--FSM state register:
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(same as for category 2 Moore, section 9.2)
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--FSM combinational logic:
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process (all) --list proc. inputs if ″all″ not supported
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begin
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case pr_state is
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when A =>
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outp <= outp_reg;
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tmax <= T1-1;
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if <condition> then
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nx_state <= B;
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elsif <condition> then
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nx_state <= ...;
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else
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nx_state <= A;
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end if;
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when B =>
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outp <= outp_reg + 1;
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tmax <= T2-1;
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if <condition> then
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nx_state <= C;
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elsif <condition> then
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nx_state <= ...;
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else
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nx_state <= B;
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end if;
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when C =>
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...
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end case;
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end process;
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--Optional output register:
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(same as for category 1 Moore, section 6.3)
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output <= outp;
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75 end architecture;
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