Hardware Reference
In-Depth Information
12.3 VHDL Template for Recursive (Category 3) Mealy Machines
The template is presented below. The only difference with respect to the Moore tem-
plate just described is in the process for the combinational logic (lines 23-57) because
the output is specii ed differently here. Recall that in a Mealy machine the output
depends not only on the FSM's state but also on the input, so
if
statements are
expected for the output in one or more states because the output value might not be
unique.
Please review the following comments, which can be easily adapted from the Moore
case to the Mealy case:
—On the Moore template for category 1, in section 6.3, especially comment 10.
—On the
enum_encoding
and
fsm_encoding
attributes, also in section 6.3.
—On possible code variations, in section 6.4.
—On the Mealy template for category 1, in section 6.5.
—On the Moore template for category 2, in section 9.2.
—On the Mealy template for category 2, in section 9.3.
—Finally, on the Moore template for category 3, in section 12.2.
1 -------------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -------------------------------------------------------------
5 entity circuit is
6 (same as for Moore, section 12.2)
7 end entity;
8 -------------------------------------------------------------
9 architecture mealy_fsm of circuit is
10 (same as for Moore, section 12.2)
11 Begin
12
13
--Timer:
14
(same as for Moore, section 9.2)
15
16
--Auxiliary register:
17
(same as for Moore, section 12.2)
18
19
--FSM state register:
20
(same as for Moore, section 9.2)
21
22
--FSM combinational logic:
23
process (all) --list proc. inputs if ″all″ not supported
24
begin
25
case pr_state is
26
when A =>
27
if <condition> then
28
outp <= outp_reg;
29
tmax
<
=
<
value
>
;
30
nx_state
<
= B;
31
elsif
<
condition
>
then
