Hardware Reference
In-Depth Information
range. Every time the pushbutton is pressed (and released),
ref
must be incremented
by one unit; however, if the pushbutton is kept pressed for
t
1
= 2 s (
T
1
clock periods)
or longer, the increment must occur automatically and at every
t
2
= 0.5 s (
T
2
clock
periods). If the maximum value is reached, the machine must stop and hold that value,
only returning to the initial state if the pushbutton is released and pressed again.
A solution (without the debouncer) is depicted in i gure 11.8b, which is simply the
basic building block of i gure 11.7b plus two extra states (E, F), added to take care of
the time-related specii cations. Note that the initial and i nal values can be chosen
freely by the designer and that the CD and EF transitions are unconditional. Again,
the machine size is independent of the number of reference values and of the time
values used in the timed transitions (the time values only affect the size of the counter
that implements the timer).
Even though
up
is an asynchronous input in i gure 11.8, a synchronizer (section
2.3) is not needed because a debouncer was included in the circuit (and the applica-
tion might not be critical anyway).
Based on section 11.6, the number of l ip-l ops needed to build the FSM of i gure
11.8b is as follows. For the state register:
M
FSM
= 6 states, so
N
FSM
= 3 if sequential, Gray,
or Johnson encoding is used, or 6 for one-hot. For the auxiliary register: needed for
ref
; because it is an eight-bit value,
N
aux
= 8. For the optional output register: not
needed, so
N
output
= 0. (If needed, the auxiliary register could be used for that because
it contains
ref
anyway.) For the timer: because
t
state_max
= 2 s, and assuming
f
clk
= 50
MHz,
T
max
= 10
7
clock cycles results, so
N
timer
= 27. Therefore,
N
total
= 38 or 41 DFFs.
11.7.4 Reference-Value Defi ner with Embedded Debouncer
This section is an extension to the section above. Because in many control applications
reference values are set by means of mechanical switches, which might require some
sort of debouncer (section 8.11.3), we want to examine the possibility of embedding
the debouncer directly into the reference-value dei ner circuit.
Three possible situations are depicted in i gure 11.9: (a) with debouncers imple-
mented as two separate circuits; (b) with the debouncers combined into a single circuit;
(c) with the debouncers embedded in the FSM that implements the reference-value
dei ner. The case in a was seen in section 8.11.3; that in b was treated in exercises 8.11
and 8.12; and that in c is discussed in this section.
The general debouncing principle seen in section 8.11.3 is summarized in i gure
11.10a (with a simplii ed representation—see i gure 1.4), which says that for the
output to change from '0' to '1' the input must remain high during
T
consecutive
clock cycles (recall that the timer is zeroed every time the machine changes its state,
so if a '0' occurs before the time has been completed, the machine returns to the initial
state, restarting the timer).
