Hardware Reference
In-Depth Information
Figure 11.9
Reference-value dei ner with up and down controls set by two pushbuttons having the debounc-
ers (a) implemented as two separate circuits, (b) implemente as a combined circuit, and (c)
embedded into the main FSM.
Figure 11.10
(a) Review of the general debouncing principle. (b) Machine of i gure 11.7d with embedded
debouncer (for the '0'-to-'1' transition only).
This principle was applied to the '0'-to-'1' ('1'-to-'0' not included) transitions of
i gure 11.7d, resulting in the state diagram of i gure 11.10b. Note the white circles
between states BC and BD, related to the debouncing procedure.
For an analysis of the number of l ip-l ops, see exercise 11.6. For another imple-
mentation, concerning the case of i gure 11.7b, see exercise 11.7.
11.7.5 Datapath Control for a Sequential Multiplier
Before we examine this example, a review of Section 3.13 is useful. Particular attention
should be paid to comment 4 at the end of that section, which is helpful here.
Figure 11.11a presents an algorithm for unsigned sequential multiplication using
only add and shift operations. It computes the product in N iterations (after a data-
load operation), where N is the number of bits in the multiplier and multiplicand,
and 2 N is the number of bits in the product. Note that the product is divided into
Search WWH ::




Custom Search