Hardware Reference
In-Depth Information
present and next states. In the timer-related declarations (lines 14-16), the value
chosen for
chirpON
and
chirpOFF
is such that the chirp and the time interval between
chirps last 0.3 s, assuming
f
clk
= 50 MHz.
The third and i nal part of the code (
statements
) is in lines 18-97. It contains three
always
blocks, described next.
The i rst
always
block (lines 21-24) is an
always_ff
that implements the timer,
using strategy #2, exactly as in the template.
The second
always
block (lines 27-29) is another
always_ff
, implementing the
machine's state register, also as in the template.
The third and i nal
always
block (lines 32-95) is an
always_comb
, which imple-
ments the entire combinational logic section. It is just a list of all states, each contain-
ing the output (
siren
) value, the value of
t
max
, and the next state. Note that in each
state the output value is unique because in a Moore machine the output depends only
on the state in which the machine is.
In this kind of application the “
1” term present in the determination of
t
max
(lines
42, 67, 73, . . .) does not make any difference, but it was maintained as a reminder of
the precise value. Also, in this kind of application possible glitches during (positive)
clock transitions are generally not a problem, so the optional output register shown
in the i nal portion of the template was not employed.
Finally, and very importantly, observe the correct use of registers and the complete-
ness of the code, as described in comment 8 of section 7.3. Observe in particular the
following: 1) all states are included; 2) the list of outputs is exactly the same in all
states, and the corresponding values are properly declared; 3) the specii cations for
nx_state
are always i nalized with an
else
statement, so no condition is left unchecked.
The total number of l ip-l ops inferred by the compiler on synthesizing this code
was 28 for sequential or Gray encoding, 29 for Johnson, and 34 for one-hot. Compare
these results against your predictions made in exercise 8.14.
Simulation results are shown in i gure 10.1.
−
Figure 10.1
Simulation results from the SystemVerilog code for the car alarm of i gure 8.21c for
chirpON
=
chirpOFF
= 3 clock cycles.
