Hardware Reference
In-Depth Information
46
end
47
B: begin
48
ssd <= 7'b1011111;
49
if (t>=T1-1) nx_state <= BC;
50
else nx_state <= B;
51
end
52
BC: begin
53
ssd <= 7'b1001111;
54
if (t>=T2-1) nx_state <= C;
55
else nx_state <= BC;
56
end
57
C: begin
58
...
59
end
60
CD: begin
61
...
62
end
63
D: begin
64
...
65
end
66
DE: begin
67
...
68
end
69
E: begin
70
...
71
end
72
EF: begin
73
...
74
end
75
F: begin
76
...
77
end
78
FA: begin
79
ssd <= 7'b0111101;
80
if (t==T2-1) nx_state <= A;
81
else nx_state <= FA;
82
end
83
endcase
84
85 endmodule
86 //-------------------------------------------------
10.5 Design of a Car Alarm (with Chirps)
This section presents a SystemVerilog-based design for the car alarm with chirps intro-
duced in section 8.11.6. The Moore template of section 10.2 is employed to implement
the FSM of i gure 8.21c. Again, either strategy #1 or #2 can be used to build the timer;
the latter was adopted in the code below.
The i rst part of the code (
module header
) is in lines 1-4. The module's name is
car_alarm_with_chirps
. Note that all ports are of type
logic
.
The second part of the code (
declarations
) is in lines 6-16. In the FSM-related dec-
larations (lines 9-11), the enumerated type
state
is created to represent the machine's
