Hardware Reference
In-Depth Information
30
elsif rising_edge(clk) then
31
if pr_state /= nx_state then
32
t <= 0;
33
elsif t /= tmax then
34
t <= t + 1;
35
end if;
36
end if;
37
end process;
38
39
--FSM state register:
40
(same as for category 1 Moore, section 6.3)
41
42
--FSM combinational logic:
43
process (all) --list proc. inputs if “all” not supported
44
begin
45
case pr_state is
46
when A =>
47
output1 <= <value>;
48
output2 <= <value>;
49
...
50
if ... and t>=T1-1 then
51
nx_state <= B;
52
elsif ... and t>=T2-1 then
53
nx_state <= ...;
54
else
55
nx_state <= A;
56
end if;
57
when B =>
58
output1 <= <value>;
59
output2 <= <value>;
60
...
61
if ... and t>=T3-1 then
62
nx_state <= C;
63
elsif ... then
64
nx_state <= ...;
65
else
66
nx_state <= B;
67
end if;
68
when C =>
69
...
70
end case;
71
end process;
72
73
--Optional output register:
74
(same as for category 1 Moore, section 6.3)
75
76 end architecture;
77 --------------------------------------------------------------
The next template is for timed Moore machines employing strategy #2 to imple-
ment the timer.
The i rst difference is in line 18, which now includes also
t
max
.
The second difference is in the process for the timer (lines 23-34), which is a copy
of the code presented in section 8.5.3.
