Hardware Reference
In-Depth Information
The third and i nal difference is in the process for the combinational logic block
(lines 40-70), which requires now the value of
t
max
to be specii ed in each state (lines
47, 59, . . .), even if the state is untimed (
t
max
= 0). This code can obviously be simpli-
i ed in several ways when there are no conditional-timed transitions and/or
t
max
is the
same in all or most states.
1 --Timed Moore machine with timer control strategy #2------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -----------------------------------------------------------------
5 entity circuit is
6 (same as template above)
7 end entity;
8 -----------------------------------------------------------------
9 architecture moore_fsm of circuit is
10
11
--FSM-related declarations:
12
(same as for category 1 Moore, section 6.3)
13
14
--Timer-related declarations:
15
constant T1: natural := <value>;
16
constant T2: natural := <value>; ...
17
constant tmax_timer: natural := <value>; -- ≥max(T1,T2,...)-1
18
signal t, tmax: natural range 0 to tmax_timer;
19
20 begin
21
22
--Timer (strategy #2, section 8.5.3):
23
process (clk, rst)
24
begin
25
if (rst='1') then
26
t <= 0;
27
elsif rising_edge(clk) then
28
if t < tmax then
29
t <= t + 1;
30
else
31
t <= 0;
32
end if;
33
end if;
34
end process;
35
36
--FSM state register:
37
(same as for category 1 Moore, section 6.3)
38
39
--FSM combinational logic:
40
process (all) --list proc. inputs if “all” not supported
41
begin
42
case pr_state is
43
when A =>
44
output1 <= <value>;
45
output2 <= <value>;
46
...
47
tmax <= T1-1;
48
if ... and t=tmax then
49
nx_state <= B;
