Hardware Reference
In-Depth Information
RG, and onward. The time values shown in the i gure (
timeRG
,
timeRY
, and so on) are for the regular operation mode, which must change to
timeTEST
if the system is switched to the test mode (not included in the state diagram for the
sake of simplicity). Note that, due to the nature of this application,
stby
can operate
in a way similar to reset (after proper synchronization/glitch removal).
Based on section 8.10, the number of l ip-l ops needed to implement this circuit is
as follows. For the state register:
M
FSM
= 5 states; therefore,
N
FSM
= 3 if sequential, Gray,
or Johnson encoding is used, or 5 for one-hot. For the optional output register: not
needed in this application, so
N
output
= 0. For the timer: knowing that
t
state_max
= 15 s
(table of i gure 8.20a) and assuming
f
clk
= 50 MHz,
T
max
= 75
RG
→
RY
→
GR
→
YR
→
⋅
10
7
clock cycles results,
so
N
timer
= 30. Therefore,
N
total
= 33 or 35.
The analysis on the need for reset and synchronizers is left as an exercise (exercise
8.13).
8.11.6 Car Alarm (with Chirps)
A car alarm was presented in section 4.2.4. The example shown here is an extension
to that one, now with chirps included to announce when the alarm is turned on (one
chirp) or off (two chirps). Because the chirps are brief siren activations, a timed
machine is now needed.
The circuit ports are shown in
i gure 8.21a. The inputs are
remt
(command from
the remote control) and
sen
(from sensors indicating intrusion) plus clock and reset.
Figure 8.21
Car alarm. (a) Circuit ports. (b) Bad (with state bypass and non-true complementarity) and (c)
good solutions.
