Hardware Reference
In-Depth Information
Figure 6.4
Simulation results from the VHDL code for the garage door controller of i gure 5.9c.
Simulation results are depicted in i gure 6.4. The encoding chosen for the states
was
sequential
(section 3.7). The states are enumerated from 0 to 7 (there are eight
states), in the order in which they were declared in lines 12-13. Be aware, however,
that some compilers reserve the value zero for the reset state; because the reset (initial)
state in the present example is
closed1
(see lines 20-21), which is the i rst state in the
declaration list, that is not a concern here.
In this simulation the sequence
closed1-closed2-opening1-opening2-open1-open2-
closing1-closed1
(see state names in the lower part of i gure 6.4) was tested. Note that
pulses of various widths were used to illustrate the fact that their width has no effect
beyond the i rst positive clock edge.
6.8 Design of a Datapath Controller for a Greatest Common Divisor Calculator
This section presents a VHDL-based design for the control unit introduced in sec-
tion 5.4.8, which controls a datapath to produce a greatest common divisor (GCD)
calculator. The Moore template of section 6.3 is employed to implement the FSM of
i gure 5.13e.
The entity, called
control_unit_for_GCD
, is in lines 5-11. All ports are of the type
std_logic
or
std_logic_vector
(industry standard).
The architecture, called
moore_fsm
, is in lines 13-80. As usual, it contains a declara-
tive part (before the keyword
begin
) and a statements part (from
begin
on).
In the declarative part of the architecture (lines 14-15), the enumerated type
state
is created to represent the machine's present and next states.
The i rst process (lines 19-26) in the statements part implements the state register.
As in the template, this is a standard code with clock and reset present only in this
process.
