Hardware Reference
In-Depth Information
13 x_out: out std_logic_vector(bits-1 downto 0));
14 end entity;
15 ------------------------------------------------------
16 architecture direct_counter of counter is
17 signal x: natural range 0 to xmax;
18 begin
19 process (clk, rst)
20 begin
21 if rst='1' then
22 x <= xmin;
23 elsif rising_edge(clk) and ena='1' then
24 if x<xmax then
25 x <= x + 1;
26 else
27 x <= xmin;
28 end if;
29 end if;
30 end process;
31 x_out <= conv_std_logic_vector(x, bits);
32 end architecture;
33 ------------------------------------------------------
6.7 Design of a Garage Door Controller
This section presents a VHDL-based design for the garage door controller introduced
in section 5.4.5. The Moore template of section 6.3 is employed to implement the
FSM of i gure 5.9c.
The entity, called
garage_door_controller
, is in lines 5-9. All ports are of type
std_logic
or
std_logic_vector
(industry standard).
The architecture, called
moore_fsm
, is in lines 11-94. As usual, it contains a declara-
tive part (before the keyword
begin
) and a statements part (from
begin
on).
In the declarative part of the architecture (lines 12-14), the enumerated type
state
is created to represent the machine's present and next states.
The i rst process (lines 18-25) in the statements part implements the state register. As
in the template, this is a standard code with clock and reset present only in this process.
The second and i nal process (lines 28-92) implements the entire combinational
logic section. It is just a list of all states, each containing the output value and the
next state. Note that in each state the output value is unique because in a Moore
machine the output depends only on the state in which the machine is.
Observe the correct use of registers and the completeness of the code as described
in comment number 10 of section 6.3. Note in particular the following:
1) Regarding the use of registers: The circuit is not overregistered. This can be observed
in the
elsif rising_edge(clk)
statement of line 22 (responsible for the inference of
l ip-l ops), which is closed in line 24, guaranteeing that only the machine state (line
23) gets stored. The output (
ctr
) is in the next process, which is purely combinational
(thus not registered).
