Hardware Reference
In-Depth Information
2) Regarding the outputs: The list of outputs (just
ctr
in this example) is exactly the
same in all states (see lines 32, 39, 46, …), and the corresponding output value is
always properly declared.
3) Regarding the next state: Again, the coverage is complete because all states are
included (see lines 31, 38, 45, …), and in each state the conditional declarations for
the next state are always i nalized with an
else
statement (lines 35, 42, 51, …), guar-
anteeing that no condition is left unchecked.
1 --------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 --------------------------------------------------------
5 entity garage_door_controller is
6 port (
7 remt, sen1, sen2, clk, rst: in std_logic;
8 ctr: out std_logic_vector(1 downto 0));
9 end entity;
10 --------------------------------------------------------
11 architecture moore_fsm of garage_door_controller is
12 type state is (closed1, closed2, opening1, opening2,
13 open1, open2, closing1, closing2);
14 signal pr_state, nx_state: state;
15 begin
16
17
--FSM state register:
18
process (clk, rst)
19
begin
20
if rst='1' then
21
pr_state <= closed1;
22
elsif rising_edge(clk) then
23
pr_state <= nx_state;
24
end if;
25
end process;
26
27
--FSM combinational logic:
28
process (all) --or (pr_state, remt, sen1, sen2)
29
begin
30
case pr_state is
31
when closed1 =>
32
ctr <= "0-";
33
if remt='0' then
34
nx_state <= closed2;
35
else
36
nx_state <= closed1;
37
end if;
38
when closed2 =>
39
ctr <= "0-";
40
if remt='1' then
41
nx_state <= opening1;
42
else
43
nx_state <= closed2;
44
end if;
45
when opening1 =>
