Hardware Reference
In-Depth Information
Figure 5.18
Figure 5.19
to access common resources. Obviously, only one of them can use the bus at a
time; for example, if P1 wants to use the bus, it issues a request (
r
1
= '1') to the
arbiter, which grants (
g
1
= '1') access only if the bus is idle at that moment. If
multiple requests are received by the arbiter, access is granted based on preestablished
priorities. Assuming that the priorities are P1
P3, draw a state transition
diagram for a machine capable of implementing this arbiter. The machine's input
and output are the vectors
r
=
r
1
r
2
r
3
and
g
=
g
1
g
2
g
3
, respectively (besides clock and
reset, of course).
>
P2
>
Exercise 5.8: Manchester Encoder
An IEEE Manchester encoder produces a low-to-high transition when the input is '1'
or a high-to-low transition when it is '0', as illustrated in i gure 5.19 for the sequence
“01001”. Note that each input value lasts two clock periods. Observe also the presence
of a
dv
bit, which dei nes the extent of the vector to be encoded (dashed lines in
y
indicate “don't care” values). To be more realistic,
dv
is produced at the same time
that the i rst valid bit is presented; additionally, a small propagation delay is included
between clock transitions and corresponding responses. Assume that the machine too
must operate at the positive clock edge.
a) Draw a state transition diagram for a Moore machine capable of implementing this
encoder.
b) Redraw the illustrative timing diagram of i gure 5.19 for your Moore machine,
including in it a plot for
pr_state
. Does the Moore circuit behave exactly as in i gure
5.19, or is
y
one clock cycle delayed?
c) Redo the design, this time employing a Mealy machine.
