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Figure 5.20
d) Repeat part b now for your Mealy solution.
e) Say that we want the output to be completely clean. Are any of the solutions above
guaranteed to be glitch-free? If not, how can glitches be removed? What happens then
with the time response?
Exercise 5.9: Differential Manchester Encoder
Figure 5.20 illustrates the operation of a differential Manchester encoder for the
sequence “01001”. Note that the shape of the output pulse remains unchanged when
the input is '0' but gets inverted when it is '1'. For example, if the last pulse was a
'1'-to-'0' pulse, the next pulse must be '1'-to-'0' if the input is '0' or '0'-to-'1' if it is
'1'. Observe the presence of a dv bit, which dei nes the extent of the vector to be
encoded (dashed lines in y indicate “don't care” values). To be more realistic, dv is
produced at the same time that the i rst valid bit is presented; additionally, a small
propagation delay has been included between the clock transitions and the corre-
sponding responses. Assume that the machine too must operate at the positive clock
edge.
a) Draw a state transition diagram for a Moore machine capable of implementing this
encoder.
b) Redraw the illustrative timing diagram of i gure 5.20 for your solution, including
in it a plot for pr_state . Does the Moore circuit behave exactly as in i gure 5.20, or is
y one clock cycle delayed?
Exercise 5.10: Time-Ordered “111” Detector
Draw the state transition diagram for an FSM that detects the sequence abc = “111”
under the constraint that it must be time ordered; that is, a = '1' must occur (and
hold), then b = '1' must also occur (and hold), and i nally, c = '1' must happen. The
circuit ports are shown in i gure 5.21a. The circuit operation is illustrated in i gure
5.21b, where x = '1' occurs when abc = “111”, but in a time-ordered fashion.
Exercise 5.11: Vending Machine
It was seen that the vending machine controller of i gure 5.10b must be improved
to avoid state bypass. Present a solution for this problem. Is it better to include wait
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