Pipeline Architecture for High Speed License Plate Character Recognition - Advances in Image and Graphics Technologies - page 80

and 10 Arabic numbers, each class contains 40 samples. In praxis, characters images
are divided into 2×2 sub-blocks, the size of each sub-block is 12×24, 20 images of each
class in the database are used for compose the training set, and others are used for
testing.
The hardware architecture is implemented with Verilog HDL utilizing Quartus II
synthesis software, the target FPGA is an Altera Cyclone II chip which contains
68,416 logic cells, 1,152,000 memory bits, and 150 embedded multipliers, and the
width of eigen space projection is 32 bit. Recognition rate of varying number of
eigenvectors (1~12) is shown in Table 1. The optimum recognition rate is 96.77%, and
the corresponding number of eigenvectors is 6.

Table 1. Recognition rate

Eigenvectors Recognition rate (%)

1 66.77

2 93.54

4 96.38

6 96.77

8 96.46

10 95.92

12 96.15

In practical implementation, ʵ is set to 6 for feature extraction. Table 2 shows
resource consumption of the hardware architecture, occupies about 36% on-chip
memory bits, and 11% embedded multipliers. With all other functions (image
input/output, memory and synchronization control, etc.), only 6% logic cells are
consumed in total.

Table 2. Resource consumption

Consumed Total on-chip

Logic cells 3782 68,416

Memory bits 412,176 1,152,000

Embedded multipliers 34 300

All character recognition functions in the pipeline architecture are run at 100 MHz,
compare it against the software which is implemented on an AMD dual-core 2.6 GHz
PC with Matlab 7.6. The recognition speed is shown in Table 3.

Table 3. Recognition speed

Hardware Software

Target device EP2C70F896C6 PC

Synthesis tool Quartus II 12.0 Matlab 7.6

Total clock cycles 21,322 --

Clock frequence 100 MHz --

Recognition time 213.2 µs 297.4 µs