A Fast Mode Decision Algorithm and Its Hardware Design for H.264/AVC Intra Prediction - Advances in Image and Graphics Technologies - page 53

Fig. 2. State transition diagram of Control Unit

3.2 Predicted Generator Module

According to the fundamentals of intra prediction, it is proved that there are many
common calculation parameters for different prediction modes, and many calculation
formulas can be achieved in a same configurable calculation unit. In conclusion, we
can obtain a configurable architecture for prediction generator module, and the
processing element (PE) array is designed to generate concurrently 16 prediction
pixels as shown in figure3.
(1) Parallel processing unit
Considering the clock frequency and the effective use of middle result regis-
ters, we proposed a parallel configurable and pipelining processing units to achieve
the prediction calculation. Each PE generates one prediction pixel by selecting the
right required reference pixel using multiplexers, and selects the right signal by a
special logically controlled by FSM. However, the circuit will become a large scale,
and requires a large capacity memory to match in the subsequent processing.
In the configurable architecture, each prediction element is composed of 3
components: the sum operation of the reference pixels, round value and shift value.
(2) Reconstructed neighbor samples memories and prediction memories
In intra prediction, the prediction processing for the current macroblock is existed
when the reconstructed samples belonging to the neighbor blocks are available. For
the real time processing of 60 fps of HD 1080p resolution, 486000 macroblocks
should be processed per second, which result in high external memory bandwidth.
This is why this work of research proposes a scheme, that a line of pixels in a frame is
stored into the FPGA internal memory (BRAM).
For the luma 16×16 and Chroma 8×8 prediction mode decision is not executed in
4×4 block level, the re-processing result in a high number of clock cycles. In order to
prevent the shortcomings, the architecture is taken into advantage of BRAMs in
FPGA to store the predicted luma 16×16 blocks and Chroma 8×8 blocks.