A Fast Mode Decision Algorithm and Its Hardware Design for H.264/AVC Intra Prediction - Advances in Image and Graphics Technologies - page 54

Fig. 3. Hardware architecture of PE array

4 Results and Comparisons with Related Work

The proposed algorithm is described in Verilog HDL and verified using Modelsim 6.5
SE. And then the Verilog RTL is synthesized to a Xilinx Virtex-5 FPGA using Synpl-
ify. The maximum clock frequency can be achieved at 184.8 MHz. In the simulation
example, when the best prediction mode of chroma 8×8 block is mode1, the simula-
tion waveform of prediction mode decision is shown in figure4. In the simulation
waveform, the mincost port represents the minimum SAD value. The best mode port
represents the best prediction mode corresponding to the minimum SAD value, which
is mode 1 in this algorithm design.

Fig. 4. The simulation waveform of intra prediction mode decision

The synthesis results of the architecture are shown in Table 5; and table 6 shows
the comparisons with related work.