CMOS Implementations of Current Conveyors - Current Conveyors: Variants, Applications and Hardware Implementations - page 71

capacitor C c . Finally, the group of MOSFETs M 9 ,M 14 ,M 10 and M 15 constitute the
second inverting transconductance stage while the M 12 ,M 13 ,M 17 and M 18 consti-
tute the third inverting transconductance stage.
Using 1.5 V supply, the test on a prototype, fabricated in a 0.35

ʼ m technology,

Ω

exhibits an input resistance lower than 100 at the X-terminal of the CCII. The

current drive capability achieved was better than 0.9 mA which is about 45 times

of the quiescent current in the output branch. The frequency response demonstrated
that the 3-dB bandwidth for the current gain between Z and X port was about
1.2 MHz and that for the voltage gain between ports Y and X as 2.4 MHz.

4.12 CMOS Rail-to-Rail Current Conveyor

To meet the requirements of wide dynamic range and wide bandwidth operations
under low supply voltage environment, the circuits employing CCs which them-
selves should have rail-to-rail operation capability are of particular interest. A
number of authors have focused on the design of such CMOS CC architectures.
One such CMOS CC architecture was advanced by Kurashina et al. in [ 32 ] and is
shown here in Fig. 4.12 . This circuit consists of a rail-to-rail complementary
differential input stage for the voltage input V Y formed by the MOSFETs M 1 -M 8
where R C1 ,R C2 ,C C1 ,C C2 have been used for phase compensation whereas the
transistors M 9 -M 12 constitute the level shifting stage. The MOSFETs M 13 and M 14
constitute the rail-to-rail class AB push-pull stage which provides an output termi-
nal which acts either as a voltage output or current input for input current I x . Finally,
the MOSFETs M 15 to M 22 create appropriate current mirrors and the two comple-
mentary Z-output terminals Z+ and Z

.

+V DD

V p

M 12 M 21

M p M 22

M 20

M 13

M 19

M 5

M 6

M 10

M 4 −Z

M 3 X

Y

+Z

M 2

M 1

M 9

M 7 M 8

R c1

R c2 M 17 M 18

M 14 M 16

V n M 15

M 11

C c1

M n

C c2

−V SS

Fig. 4.12 CMOS CC architecture was advanced by Kurashina et al. (Adapted from [ 32 ] © 2002
IEICE)