Hardware Reference
In-Depth Information
+V
+V
+V
+V
Q
18
Q
20
Q
19
Q
23
Q
24
Q
15
Q
17
Q
16
Q
21
Q
22
Cascode Current Repeater
Cascode Current Mirror
+V
I
0
I
1
Q
5
Q
6
Q
1
Q
2
i
y
(t)
V
y
(t)
i
x
(t)
i
z
(t)
V
x
(t)
V
z
(t)
Q
3
Q
4
Q
7
Q
9
Q
8
Q
11
Q
10
Q
12
Q
14
Q
13
−V
Fig. 3.16 CCI+ implementation proposed by Fabre et al. [
15
]
Another design of the CCI+ proposed by Fabre et al. [
15
] is shown in Fig.
3.16
which was derived from a translinear current convertor described previously by
Fabre in [
16
]. In this circuit, the PNP current mirror consisting of transistors Q
15
to
Q
20
forces the DC bias current I
0
to flow through the collectors of Q
1
and Q
2
thereby
ensuring V
x
(t)
of the transistors are large enough,
the application of the
translinear principle
on the mixed translinear loop consisting
of Q
1
-Q
2
-Q
3
-Q
4
implies that the collector currents of the transistors Q
3
and Q
4
would have the same value I
0
and consequently i
y
(t)
¼
V
y
(t). Now assuming that the
β
i
x
(t). The mechanism to
convey to port Z a current equal to the input current i
x
(t), consists of a modified
Wilson current mirror based current repeater consisting of transistors Q
9
-Q
10
-Q
11
-
Q
12
-Q
13
-Q
14
and a cascode current mirror consisting of PNP transistors Q
21
-Q
22
-
Q
23
-Q
24
with a current source I
1
added which is to be adjusted to balance out the
offsets resulting from non-identical values of
¼
β
of NPN and PNP transistors in the
ALA200 transistor array from AT&T.
With
A, the circuit
dissipates about 20 mW, exhibits the current gains for Y and Z ports as 1.012 and
0.978 respectively with deviation in the current gains remaining less than 5 % for
5 V DC power supplies and a DC bias current I
0
of 500
ʼ
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