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a
b
+15V
+15V
+15V
+15V
2k
2k
2k
2k
2k
2k
5k
5k
+15V
+15V
Z
X
X
Z
−15V
Y
−15V
5k
5k
Y
2k
2k
2k
2k
2k
2k
−15V
−15V
Fig. 3.6 CCII implementation using bipolar transistors (a) CCII+ (b) CCII
[
6
]
implementations proposed by Matsuura et al. [
40
] which are shown in Fig.
3.6
.
These circuits were realized using 2SA71 PNP transistors and 2SC1327 NPN
transistors.
3.2.5 Surakampontorn and Thitimajshima Electronically-
Controlled Conveyor (ECC)
Surakampontorn and Thitimajshima [
8
] presented a generalized current conveyor
known as electronically tunable second generation current conveyor (ECCII) whose
current transfer ratio between port currents i
z
and i
x
can be varied electronically.
The circuit presented by them however provides two complementary Z outputs
thereby realizing CCII+ and CCII
in the same circuit configuration which was
claimed to be suitable for monolithic integrated circuit implementation. The basic
principle of the circuit can be explained on the basis of the simplified schematic of
Fig.
3.7
. In this circuit, Q
1
and Q
2
constitute a differential pair with bases of
transistor of Q
1
and Q
2
constituting port Y and X respectively. It is seen that the
current source of value I
1
/2 ensures that collector current of Q
1
and Q
2
would be
equal where from, with identical transistors, it follows that their base emitter
voltages which are also equal will cancel out thereby ensuring v
x
¼
v
y
. Through
the current source I
2
, the collector current of Q
3
becomes I
2+
i
x
. The differential
current amplifier through the current mirror produces an output current which is
I
2
+Ai
x,
thus, yielding i
z
¼
Ai
x
.
A fully integrable circuit configuration of the ECCII based upon this idea using
NPN transistor array LM3046, matched discrete PNP transistors and integrated
current sources LM334 to provide the DC bias currents has also been described by
Surakampontorn and Thitimajshima in the same paper [
8
].
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