Hardware Reference
In-Depth Information
i
fR
DS
<<
R
1
R
2
ð
R
1
Þ
T
r
¼
T
3
T
2
R
DS
C
ln 1
þ
R
1
ð
15
:
49
Þ
R
2
R
DS
From the above, it is easy to visualize that, since R
DS
(turn-on resistance of the
analog switch) is usually much larger than R
1
, the recovery time of the second
monostable circuit will be much shorter than the first one.
The effectiveness of both the circuits has been confirmed through SPICE
simulations as well as hardware implementations by realizing DVCC with
AD844AN ICs and using CD4066 as the analog switch where from the effective-
ness of the second circuit in shortening the recovering time has been confirmed in
both the cases.
15.6.4 Chien
'
s Relaxation Oscillators
Two circuits for realizing relaxation oscillators using DVCC were presented by
Chien in [
15
]. The first circuit can generate a symmetrical square wave with 50 %
duty cycle while the second circuit can further control the duty cycle by adjusting
the tuning factor of the potentiometer. These circuits are shown in Fig.
15.12
.
The operation of the circuit of Fig.
15.12
a can be explained as follows: Let us
assume that V
0
is in the high state i.e., V
0
¼
V
0
+
if we take R
1
>
R
2
then
,
I
X
is more
positive than I
Z
and consequently, V
0
is guaranteed to be in the state V
0
+
. The
capacitor charges exponentially from low threshold (V
LT
) to high threshold (V
HT
).
When capacitor voltage becomes slightly greater than V
TH
, this also implies that
now I
X
would have become slightly less than I
Z
, as a consequence of which V
0
switches from V
0
+
state to V
0
state. From a routine analysis [
15
], the two threshold
voltages are found to be:
V
0
þ
and
V
TL
¼
V
0
þ
R
1
R
2
R
1
R
2
V
TH
¼
1
1
ð
15
:
50
Þ
If we consider the total time period in which the output waveform remains high as
T
1
, from a straight forward analysis, its value is given by:
2
R
2
R
1
T
1
¼
R
1
C
ln
1
ð
15
:
51
Þ
Similarly, the time period in which the output wave remains in low state i.e., V
0
is
found to be:
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