Hardware Reference
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a
b
I
z
I
z
y
2
z
V
0
y
2
z
V
0
DVCC
DVCC
y
1
y
1
x
x
I
x
I
x
D
2
D
1
R
1
R
2
R
2
k
R
p
+
−
v
c
Rp
C
+
−
v
c
C
c
V
0
(t)
V
+
V
TH
V
c
(t)
V
TL
V
−
T
on
T
off
(off duty cycle period)
(on duty cycle period)
T
1
T
2
Fig. 15.12 The relaxation oscillators using a single DVCC and their relevant waveforms [
15
](a)
circuit with 50 % duty cycle (b) circuit with variable duty cycle (c) corresponding waveforms
2
R
2
R
1
T
2
¼
R
1
C
ln
1
ð
15
:
52
Þ
Thus, the frequency of the output square wave is found to be:
1
T
1
þ
1
f
0
¼
T
2
¼
ð
15
:
53
Þ
2
R
2
2
R
1
C
ln
R
1
1
A slightly modified form of this circuit to facilitate non-50 % duty cycle
(Fig.
15.12b
) obtained by splitting the resistance R
1
in to two parts through a
potentiometer (kR
P
) and ensuring that during the charging and discharging of the
capacitor C only one of these two parts is coming into picture. From the diagram, it
can be seen that the diode D
1
is ON and diode D
2
is OFF during the charging of the
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