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a
I B1
I B2
A
V 1
I 1
z +
y 1
y 1
y 2
y 3
z
CCDDCC3
y 2
y 3
z +
CCDDCC1
V 2 I 2
z +
x
x
B
C
I B3
y 2
z +
CCDDCC3 y 1
y 3
x
b
Fig. 14.24 Grounded capacitor floating capacitance multiplier (Adapted from [ 46 ]
2011
Elsevier) (a) The circuit configuration (b) Variation of the magnitude of the realized equivalent
capacitance
©
The workability of the capacitance multiplier was confirmed by realizing the
circuit using the CCDDCCs by the CMOS implementation of [ 60 ] (reproduced also
in Fig. 4 of [ 46 ]). The model parameters of TSMC 0.25
μ
m CMOS technology were
used with the circuit biased with
1.25 V DC. The magnitude function of the
simulated capacitance shown in Fig. 14.24 confirms the variability of the realized
capacitance value through the bias current I B2 .
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