Second Generation Applications of Other Types of Current Conveyors in Realizing Synthetic Impedances - Current Conveyors: Variants, Applications and Hardware Implementations - page 482

a b

y 1 y 2

R 1

I 1 I 2

z −

DO-DDCC

V 2 y 1

z +

V 1

z −

I in

MDO-DDCC

y 3

y 3

V in y 2

x

z +

x

R 2

C

R 1

R 2

C

Fig. 14.25 (a) Floating lossy inductance simulator using single DO-DDCC (b) Grounded lossless
inductance simulator using MDO-DDCC [ 47 ]

14.21 Floating Lossy Inductance Simulators Using a Single
DO-DDCC and a Grounded Capacitor

Figure 14.25 shows a floating lossy inductance simulator and a grounded lossless
inductance simulator proposed by Ibrahim et al. in [ 47 ] employing a dual-output
DDCC (DO-DDCC) and a modified DO-DDCC (MDO-DDCC). The circuit of
Fig. 14.25a realizes a floating lossy inductance using two resistors and a grounded
capacitor employing a DO-DDCC while Fig. 14.25b simulates a grounded lossless
inductance using two resistors and a grounded capacitor using a MDO-DDCC.
Assuming ideal DO-DDCC, the short circuit admittance matrix of the circuit of
Fig. 14.25a can be obtained as:

1 where R eq ¼

1
R eq þ

1
sL eq

1

½ ¼ Y R 1 R 2 k and L eq ¼ CR 1 R 2 ð 14 : 46 Þ

11

Thus, from equation ( 14.46 ), a floating parallel R-L is realized.
Similarly, a routine circuit analysis of the circuit of Fig. 14.25b gives its input
impedance as:

V in
I in ¼

2 sCR 2 Z in ¼ for R 1 ¼ R 2 ¼ R ð 14 : 47 Þ

Therefore, from equation ( 14.47 ), it is seen that a grounded lossless inductance of
value L eq ¼ 2 CR 2 has been simulated.

The SPICE simulations have indicated that using DO-DDCC and MIDO-DDCC
obtained from modifications of the CMOS DDCC architecture of [ 61 ] with bias
voltage of m TSMC CMOS technology,

the operational frequency range of the FI has been found to be 10-400 KHz and that
of the GI as 5-700 KHz.

1.5 V DC and model parameters of 0.35 μ