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I 2
R 1
V 2
I 1
y 1
x
y 1
V 1
DVCC x
DVCC
y 2
R 2
z
y 2
z +
C 1
Fig. 14.19 Simulation of FI using DVCCs proposed by Horng (Adapted from [ 39 ]
2010
©
Springer)
I 2
I 1
y 1
z
V 2
V 1
x
DVCC
y 2
z +
z +
y 1
z
DVCC
y 2
x
y 2
y 1
y 3
Fig. 14.20 Floating simulator proposed by Yuce [ 40 ]
14.18 Lossless Grounded Inductor Using a Single FDCCII
and Three Grounded Passive Elements
FDCCII has already been defined and characterized in an earlier chapter of this
monograph. In this section, we present an application of the FDCCII in the
realization of a grounded inductance employing a minimum number of grounded
passive elements without any component-matching condition. Figure 14.21 shows a
circuit configuration using a single FDCCII and three grounded passive components
proposed by Kacar [ 41 ].
A routine circuit analysis (assuming ideal FDCCII) of this circuit gives the
following expression of its input impedance: Z in ¼
sCR 1 R 2 . Thus, an inductor of
value L eq ¼
CR 1 R 2 has been simulated.
The circuit has been tested in SPICE using the CMOS FDCC of [ 59 ] with MOS
transistors simulated using TSMC 0.35
μ
m process model parameters and
 
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