Second Generation Applications of Other Types of Current Conveyors in Realizing Synthetic Impedances - Current Conveyors: Variants, Applications and Hardware Implementations - page 476

Fig. 14.18 Simulation of
grounded inductance using
a single DXCCII proposed
by Kacar and Yesil
(Adapted from [ 34 ] © 2010
Elsevier)

y

z p

C 1 DXCCII +

x n x p z n

R 2

R 1

Z in

14.17 FI Simulators with Only Two DVCCs

In 2010, Horng [ 39 ] presented a FI configuration employing two DVCCs, two
resistors and a grounded capacitor which did not require any component matching
conditions. Assuming ideal DVCCs, the short circuit admittance matrix of the
circuit, through a routine analysis, is found to be:

1

1
sC 1 R 1 R 2

1

½ ¼ Y ð 14 : 35 Þ

11

Thus, from above equation, a lossless FI is realized with its inductance value
L eq ¼ C 1 R 1 R 2 .

The circuit shown in Fig. 14.19 , although simulates a FI without any component
matching condition, but employs one floating resistor. Yuce in [ 40 ] presented
another configuration, shown here in Fig. 14.20 , which employs exactly the same
number of active and passive elements and exhibits the same properties but uses all
grounded components. This circuit topology can simulate FI, FC and FDNR
elements by selecting appropriate passive elements (resistor (s) or capacitor (s)).
Assuming ideal DVCCs, a straight forward analysis of this simulator yields the
following short circuit admittance matrix:

1

y 1 y 2
y 3

1

½ ¼ Y ð 14 : 36 Þ

11

From the equation ( 14.36 ) the various floating elements can be realized as follows: an
FI is realized by choosing y 3 as a capacitors with remaining admittances as resistors; a
floating capacitor is realized by choosing y 1 as a capacitor with y 2 ,y 3 being resistors;
and FDNR is realizable by having C 1 ,C 2 as capacitor with y 3 as a resistor.
To verify the workability of the proposed floating simulator of Fig. 14.20 , it was
simulated [ 40 ] in SPICE using 0.35 m TSMC CMOS technology parameters and

the DVCC structure based upon that in [ 58 ], with DC bias voltage of

μ

1.5 V.
Component values were chosen to realize an inductance value of 0.1 mH and the
magnitude and phase plots were obtained. Very good correspondence between
theoretical and simulated plots has been observed up to a frequency of about
20 MHz.