Hardware Reference
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Fig. 14.15 Electronically
controllable FI simulator
proposed by Sagbas
et al. (Adapted from [ 32 ]
© 2009 Elsevier)
I 0
I 1
V 1
z
x
+
DO-CCCII
I 2
y
V 2
z+
+
I B
C
g m
OTA
+
14.14 Resistor-Less Simulated FI Using DXCCII
Figure 14.16 shows a resistor-less simulated FI using three dual -X CCIIs
(DXCCII), three NMOS transistors (operating in triode region) and a grounded
capacitor propose by Saad and Soliman in [ 37 ]. Since drain and source terminals of
all the three MOSFETs have complementary signals this enables cancellation of the
square non-linearity in the expression for drain current in all the three cases and
each MOSFET, therefore, realizes a linear voltage-controlled-resistor whose value
is given by
1
μ n C ox L i V Gi
R i ¼
ð
14
:
26
Þ
2
ð
V th
Þ
Furthermore, since M 2 and M 3 have a common gate voltage V G2 , it therefore
follows that R 2 ¼
R 3 .
With the above in mind, the equations for the 2-port can be written as:
μ n C ox W
L
I 1 ¼
I Z 2 A ¼
I X 2 A ¼
I D 1 A ¼
2
ð
V G 1
V th
Þ
V 3
ð
14
:
27
Þ
1
Similarly
I 2 ¼
I Z 1 A ¼
I X 1 A ¼
I D 1 A ¼
I 1
ð
14
:
28
Þ
The current in the capacitance (I C ) is given by:
I C ¼
ð
I Z 1 C þ
I Z 2 B
Þ ¼
ð
I X 1 C þ
I X 2 B
Þ ¼
ð
I D 2 C þ
I D 3 B
Þ
V G 2
2 ¼
μ n C ox W
for W
L
W
L
¼
ð
V th
Þ
ð
V 1
V 2
Þ
ð
:
Þ
2
14
29
L
3
Therefore, the voltage across the capacitor (V 3 ) will be obtained as
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