Second Generation Applications of Other Types of Current Conveyors in Realizing Synthetic Impedances - Current Conveyors: Variants, Applications and Hardware Implementations - page 468

I 1 I 2

z−

V 1 x V 2

DO-CCII

y z+

y

Admittance

Y g

CCII −

z

x

Y 1

Y 2

y

x

CCII +

z

Fig. 14.10 General Configuration for converting grounded admittance into the floating admit-
tance proposed by Yuce et al. (Adapted from [ 20 ] 2006 Springer)

©

Taking into account the non-idealities of the CCs, namely, I ( z + ) j ¼ ʱ j I xj ( j ¼ 1, 3),

I ( z ) n ¼ ʳ n I xn ( n ¼1, 2), I ym ¼0 and V xm ¼ ʲ m V ym ( m ¼1, 2, 3), the short circuit

admittance matrix becomes

y g

y 2
y 1 ʱ 1 ʲ 1 ʲ 2 ʳ 2

1 ʲ 1 ʲ 3

½ nonideal ¼ Y ð 14 : 17 Þ

ʳ 1 ʳ 1 ʲ 1 ʲ 3

It is clear from the above equation that no lossy term appears in this short circuit
admittance matrix even under non-ideal conditions.
The workability of the proposed configuration was tested using the CMOS
DO-CCII presented by the authors themselves (see Fig. 3 of [ 20 ]), biased
with

m
TSMC CMOS technology parameters. Simulation results of a 3rd order
Butterworth filter designed by using the proposed simulator, for a cut-off frequency
of 159.15 KHz confirmed the validity of proposed circuit.

1.5 V DC supply simulations were performed in SPICE using 0.35 μ

14.10 Compensated Negative Impedance Converter

Yuce [ 25 ] proposed two negative impedance converters (NIC) using two CCs and a
resistor. The configuration shown in Fig. 14.11a is comprised of two DO-CCIIs and
is capable of reducing both non-ideal gain and parasitic impedance effects simul-
taneously. The circuit of Fig. 14.11b employs three CCII + s along with a resistor
but can reduce only parasitic impedance effects. Since only plus type CCIIs are
used in this structure, the configuration can be realized with commercially available