Hardware Reference
In-Depth Information
The phase difference (
/2, thus,
both V 02 ( s ) and V 01 ( s ) are in quadrature. Similarly, the two output currents I 02 ( s )
and I 01 ( s ) can be related as:
ˆ
) between V 02 ( s ) and V 01 ( s ) is found to be
ˆ¼ˀ
I 02 s
ðÞ
I 01 s
1
sR 3 C 3
ðÞ ¼
ð
13
:
27
Þ
The phase difference (
ˆ
) between I 02 ( s ) and I 01 ( s ) is seen to be:
ˆ¼ˀ
/2, thus,
ensuring that both I 02 ( s ) and I 01 ( s ) are also in quadrature.
From the above analysis, it is seen that the oscillator circuit is capable of
providing both VM and CM quadrature signals simultaneously.
SPICE simulations were carried out to check the validity of the proposed circuit
using MOCC implementations based on those in [ 56 ] using 0.18
m level
3 MOSFET parameters from TSMC. The circuit performance was found to be in
good agreement with the theoretical values.
There are several other publications which deal with ideas related to the one
discussed here, for instance, for MOCC- based oscillators see [ 5 , 21 , 36 , 40 , 47 , 52 ]
and for MOCCC-based oscillators see [ 4 , 6 , 16 , 25 , 29 , 30 , 37 , 49 ].
μ
13.11 VM/CM QO Using FDCCII
A more flexible and versatile FDCCII-based SRCO was proposed by Horng, Hou,
Chang, Chou, Lin in [ 20 ] which is shown in Fig. 13.10 which has all the features of
the earlier circuits but in addition, this circuit, with one additional Z-terminal
incorporated with the FDCCII architecture, is able to provide two explicit current
mode outputs which are in quadrature to each other.
The CO and FO for this circuit are given by:
ð
:
Þ
CO
:
R 1 ¼ R 2
13
28
r
1
C 1 C 2 R 3 R 2
FO
: ω 0 ¼
ð
13
:
29
Þ
Thus, CO can be controlled by R 1 and FO can be varied independently through R 3 .
Analyzing this QO taking into account the various non-idealities such as the
voltage tracking errors and current tracking errors, the terminal relationships of
voltages and currents are found to be governed by the following equations:
V xa ¼ ʱ a 1 v y 1 ʱ a 2 v y 2 þ ʱ a 3 v y 3 , V xb ¼ʱ b 1 v y 1 þ ʱ b 2 v y 2 þ ʱ b 4 v y 4 i y 1 ¼
i y 2
¼
i y 3 ¼
i y 4 ¼
0, i zai ¼ʲ ai i xa
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