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a
B
y
1
z+
z+
z+
y
2
y
2
I
3
C
2
DVCC2
y
2
z+
DVCC1
DVCC3
y
1
I
1
I
2
I
4
xz+
x z−
A
y
1
z+
x
R
2
R
3
C
1
R
1
b
DVCCs, see
20uA
I4
I2
I3
I1
0A
−20uA
0s
0.5us
1.0us
Time
I (VZ1)
I (VZ2)
I (VZ3)
I (VZ3I)
Fig. 13.7 CM QO proposed by Maheshwari and Chaturvedi (Adapted from [
45
]
©
2011 John
Wiley & Sons, Ltd.) (a) The circuit configuration (b) The four quadrature current outputs at 1 MHz
1
=
2
1
C
1
C
2
R
3
1
R
2
1
R
1
FO
:
ω
0
¼
provided
R
1
>
R
2
ð
13
:
18
Þ
Hence, from the above equations, it is clear that FO can be controlled by R
2
independently. The four quadrature output currents are given by I
4
¼
I
3
,
I
2
¼
I
1
and I
3
¼
j
ω
R
2
C
2
I
2
, thus for
ω
R
2
C
2
¼
1, all the quadrature outputs have
equal amplitude.
The operation of the circuit was verified by SPICE simulations using CMOS
DVCCs realizable in 0.5
m CMOS technology with level 3 MOSFET parameters
and with DC biasing supply taken as
μ
2.5 V DC, component values chosen to
achieve an oscillation frequency of 1.02 MHz. The SPICE generated frequency was
found to be 1.0 MHz. The error in frequency was merely 1.9 %, with % THD of
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