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Fig. 13.6 CM SRCOs
proposed by Chang
et al. [
11
]
a
y
1
y
2
y
4
y
3
z−
x+
FDCCII
z+
x−
z+
I
0
R
3
R
1
R
2
C
2
C
1
b
y
2
y
3
y
4
y
1
z+
x−
FDCCII
z−
x+
z+
I
0
R
3
R
1
R
2
C
2
C
1
The two oscillators described above were simulated in SPICE by realizing the
CMOS FDCCII using the implementation from [
55
] using 0.5
μ
m level 3 CMOS
process parameters. Additional current mirrors were used to produce additional
Z-terminals. The biasing used was
5 V DC. The components were chosen to get
the theoretical frequency as 2.25 MHz whereas simulations exhibited the frequency
as 2.24 MHz thus, establishing the practical viability of the proposed circuits.
13.8 CM Quadrature Oscillator (QO) Using DVCCs
In 2011, Maheshwari and Chaturvedi [
45
] proposed high output impedance CMQO
using three DVCCs and four grounded passive elements. The circuit has the
flexibility to generate three more QOs by appropriate connections of input termi-
nals. Assuming ideal DVCCs (DVCC has already been defined in earlier chapter),
the CE of the proposed QO, as shown in Fig.
13.7
, is given by:
1
C
1
R
1
1
C
2
R
3
1
C
1
C
2
R
3
1
R
2
1
R
1
s
2
þ
s
þ
¼
0
ð
13
:
16
Þ
from which the expressions for CO and FO are obtained as:
CO
ð
C
2
R
3
C
1
R
1
Þ
0
ð
13
:
17
Þ
:
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