Second Generation Controlled Current Conveyors (CCCII) and Their Applications - Current Conveyors: Variants, Applications and Hardware Implementations - page 299

Fig. 9.57 A BiCMOS
CCCII with negative
Rx [ 55 ]

+V

:1 :1 :2

M 5

M 4

M 6

I z

I x

Q 2

Z

Y Q 1 X

I B

:1 :1 :1

M 1

M 3

M 2

−V

<<

If (V x -V y ) 2V T the above equation can be approximated as:

I B V x

V y
2 V T

I x ¼ ð 9 : 79 Þ

which implies that with Y-terminal grounded the input resistance looking into the
terminal-X is given by:

2 V T
I B

R x ¼ ð 9 : 80 Þ

For the circuit of Fig. 9.57 , a similar analysis shows that in this case the intrinsic
resistance R x is given by:

2 V T
I 0

R x ¼ ð 9 : 81 Þ

SPICE simulation of this circuit using transistors of the type AMS S35 BiCMOS
0.35 μ m process with the CCCII biased with 1.5 V, the parasitic resistance of the

X-port can be tuned from 1.03 to 51.6 K ʩ when the biasing current I B changes

from 1 to 50 A for both the circuits. The three dB bandwidth of these structures

was found to be around 550 MHz for bias current of I B ¼

μ

10 μ A. The power

dissipation of the circuit was found to be of the order of 75 W which is clear

advantage over the CCC structures made from BJTs exclusively.
Chaisricharoen et al. [ 3 ] presented a novel balanced differential pair structure for
realizing CCCII which is shown here in Fig. 9.58 . The classical translinear structure
shown in Fig. 9.2 was also studied for comparison.
From detailed mathematical and simulation study it has been found that for a DC
bias current 50

μ

μ

A. this architecture exhibits a current gain of 0.991, a voltage gain
of 0.9915 with 3 dB bandwidth of both in excess of 450 MHz and the X-port input