Basic Analog Circuit Building Blocks Using CCs and Application of CCs in Impedance Synthesis - Current Conveyors: Variants, Applications and Hardware Implementations - page 110

CCII+

z

y

x

Z 5

CCII+ CCII+

z

CCII+

1

y
x

x
y

2

z y

x

Z 2

z

Z 3

Z 4

CCII+

x

z

Z 1

y

Fig. 5.32 A floating generalized impedance simulator due to Pal [ 108 ]

Fig. 5.33 A method for
compensating for the series
losses of the simulated
floating inductor proposed
by Ferri et al. [ 104 ]

I out

B

CCII 1

I in

A

y

z +

y
x

x

z

+

CCII 2

R 02

R 01

C

CCII 6

y

+ z

y
x

x

+ z

C CCII 3

R 1

R 2

x

CCII 5

z

+

x
y

y

D

z

+

CCII 4

Considering the various parasitic impedances of the CCIIs particularly modeling
the Z-port parasitics by R z /(1/sC z ) and Y-port input impedance as C y, analysis has
shown that the equivalent floating impedance realized by the circuit is given by

R 1 R 2
R Z

Z eq ¼ 2 R x þ 2 C T R 1 R 2 ð 5 : 42 Þ

where C T represents the effective total capacitance at the node connecting Z-port of
CCII+ 3 and Y-port CCII+ 6 i.e. C T ¼

(C + C Z3 +C Y6 ) . From the analysis, it follows
that the condition for theoretical zeroing of the series resistance R S is:

R 1 R 2
R Z ¼

2 R x ð 5 : 43 Þ