Link-Level Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 28

free slots
counter

a

ready

update

valid

data

sender

receiver

free slots
counter

b

ready

ready

update

valid

valid

less
slots

EB

data

data

receiver

sender

c

ready
valid

ready

valid

EB EB EB EB

data

receiver

sender

Fig. 2.16 The replacement of pipeline registers with 2-slot EBs on the link

In general, if k pairs of forward and backward registers are replaced by k 2-slot
EBs, L f and L b are reduced by k. Thus, the worst case buffering at the receiver
reduces from 2.L f C L b 1/ to 2..L f k/ C .L b k/ 1/.Ifwesumto
this number the amount of buffering present on the link, i.e., the k 2-slot EBs, we
end up having 2.L f C L b 1/ 2k buffers in total (both at the receiver and on
the link). Therefore, under ready/valid flow-control the use of EBs in the place of
pipelining stages distributed across the link is always beneficial in terms of buffering
and should be always preferred.

2.5.3 Pipelined Links and Credit-Based Flow Control

The equivalent flow control model for credit-based flow control on pipelined links
is depicted in Fig. 2.17 . In this case, the ready signal produced by the credit counter
and the valid signal that consumes the credits are generated locally at the sender
with zero latency. On the contrary, the credit update signal reaches the credit counter
through L b registers. The same holds also for the data in the forward direction that
pass through L f registers to get to the sender. At this point a critical detail needs to
be pointed out. With ready/valid handshake both the valid signal that decreased the
number of free slots and the associated data had to go through the same number
of registers after leaving the sender. However, in this case, the valid signal that
consumes the credit sees zero latency, while the data arrive at the receiver after L f