Link-Level Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 29

free slots
counter

ready Lb registers

update

...

valid

...
...

data

Lf registers

sender receiver

Fig. 2.17 The abstract flow-control model of a pipelined link using credit-based flow control

cycles. Therefore, credit consumption and data transmission experience different
latencies. This detail will be extremely useful in understanding how to compute
the required number of buffers for achieving full throughput in pipelined router
implementations described in later chapters.
The throughput of transmission is closely related to the number of credits used
by the sender and the number of clock cycles that pass from the time a credit update
leaves the sender until the first new word that consumes this returned credit reaches
the input buffer of the receiver.
This relation is illustrated by the examples shown in Fig. 2.18 . In the first case,
the sender has only one credit available (possibly meaning that the receiver has only
1 buffer slot). It directly consumes this credit and sends out a new word in cycle 0.
Once the word reaches the receiver it is immediately drained from the receiver's
buffer and a credit update is sent in the backward direction. The update needs one
cycle to reach the sender. Immediately the source consumes this credit update by
sending out a new word. Due to the forward and the backward delay of the data
and the credit-update signal, the receiver is utilized only once every 3 cycles. By
increasing the available credits to 2 that directly reflect more slots at the input buffer
of the receiver, this notification gap is partially filled and the throughput is increased
to 2/3. Finally, if the sender has 3 credits available the flow-control notification
loop is fully covered and the transmission achieves 100 % throughput keeping the
receiver busy in each cycle.
In the general case of having a L f registers in the forward path and L b registers
in the backward (credit update) path the minimum number of buffers needed at the
receiver under credit-based flow control to guarantee lossless operation and 100 %
throughput is L f C L b . Lossless operation is offered by default when using credit-
based flow control without a minimum buffering requirement, since the sender
does not send anything when there is not at least one available position at the
receiver side. As far as maximum throughput is concerned, when the receiver sends
backwards a credit update, a new word will arrive at the receiver that consumed this
credit after L f C L b cycles (L b cycles are needed for the credit update to reach
the sender plus L f cycles for the new word to reach the receiver). Therefore, the
number of words that will arrive at the receiver in a time window of L f C L b cycles
is equal to the number of credit updates sent backwards leading a throughput of
#credit u pdates
L f C L b

. Full throughput requires the number of credit updates being equal to

L f C L b reflecting an equal number buffer slots at the receiver.