Link-Level Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 25

Fig. 2.15 An abstract model of a pipelined link with L f registers in the forward direction and L b
registers in the backward direction governed by the ready/valid flow control

link. 2 The equivalent flow-control model for the ready/valid handshake is shown
in Fig. 2.15 . The slot counter that belongs to the receiver measures the number of
available buffer slots. The slot counter gets updated (incremented) with zero latency,
while it gets decremented (a new valid word arrives at the receiver) with a delay of
L f cycles relative to the time that a new word has left the sender. Also, the ready
signal that is generated by the slot counter reaches the sender after L b cycles. Please
note that once the ready signal reaches the sender it can be directly consumed in the
same cycle thus not incurring any additional latency. Equivalently, at the receiver,
the arrival of a new word can stop the readiness of the receiver in the same cycle.
This behavior at the sender and at the receiver is depicted by the dotted lines in
Fig. 2.15 .
At first, we need to examine how many words the buffer of the receiver can host
to allow for safe and lossless operation. Let's assume that the receiver declares its
readiness via the ready signal; ready is set to 1 when there is at least one empty slot,
e.g., freeSlots>0. When the buffer at the receiver is empty, the counter asserts the
ready signal. The sender will observe the readiness of the receiver after L b cycles
and immediately starts to send new data by asserting its valid signal. The first data
item will arrive at the receiver after L f C L b cycles. This is the first time that
the receiver can react by possibly de-asserting its ready signal. If this is done, i.e.,
ready 0, then under the worst case assumption, the receiver should be able to

accept the L f 1 words that are already on the link plus the L b words that may
arrive in the next cycles; the sender will be notified that the receiver is stalled L b
cycles later. Thus, once the receiver stalls, it should have at least L f C L b buffers
empty to ensure lossless operation.
Even if we have decided that L f C L b positions are required for safe operation
the condition on which the ready signal is asserted or de-asserted needs further
elaboration. Assume for example that the receiver has the minimum number of
buffer slots required, i.e., L f C L b . We have shown already that once the ready
signal makes a transition from 1 to 0 it means that in the worst case L f C L b words

D

2 The internal latency imposed by the sender and receiver can be included in L f

and L b

respectively.