Link-Level Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 24

R

free slots
counter

ready

update

valid

data

sender ABC receiver D

Fig. 2.14 An example of data transfers on a pipelined link between a sender and a receiver
governed by ready/valid flow control

the case of pipelined links, the FIFO buffer at the receiver's side needs to be sized
appropriately in order to guarantee safe lossless operation, i.e., every in flight word
finds a free buffer slot to use.

2.5.1 Pipelined Links with Ready/Valid Flow Control

The latency experienced by the forward and the backward flow control signals affect
not only the correct operation of the link but also the achieved throughput, i.e., the
number words delivered at the receiver per cycle. The behavior of the flow control
mechanism and how the latency and the slots per buffer interact will be highlighted
in the following paragraphs.
Let L f and L b denote the number of pipeline registers in the forward and
in the backward direction, respectively, in the case of a pipelined flow-controlled