Hardware Reference
In-Depth Information
flit ID
data
isHead
isTail
valid
VC id
log
2
V
update
VC id
log
2
V
VC flow control
with credits
Fig. 6.4
When a physical channel supports many VCs the wires of a link that connect a sender
and a receiver besides the flit's data and id should also include the necessary signals for VC-based
flow control: a valid bit and a VC id that identify the outgoing flit and an update bit together with
the corresponding VC id that addresses the VC of the returned credit
Fig. 6.5
A baseline
VC-buffer architecture for
3VCs built by just replicating
one 2-slot EB per VC and
including an arbiter and a
multiplexer at the read side of
the VC buffer
din
dout
EB
EB
vout[1]
rin[1]
vout[2]
rin[2]
vout[3]
rin[3]
vin[1]
rout[1]
EB
vin[2]
rout[2]
vin[3]
rout[3]
any dependencies across VC, e.g., if the buffer of a certain VC is full to stop the
transmission of flits from another VC. Examples of such dependencies arising from
sharing the buffers used for the VCs will be discussed in the following sections.
6.2
Virtual-Channel Buffers
In the simplest form of single-cycle links the valid and the backpressure information
needs one cycle to propagate in the forward and in the backward direction.
Therefore, in a single-cycle channel without VCs, a 2-slot elastic buffer (EB) would
suffice to provide lossless operation and 100 % throughput. Equivalently, a primitive
VC buffer can be built by replicating one 2-slot EB per VC, and including a
multiplexer, following the connections shown in Fig.
6.5
for the case of 3 VCs. Each
EB will be responsible for driving the corresponding ready(i )/valid(i ) signals while
all of the them will be connected to the same data wires on the write side. When
more buffering space is required a FIFO buffer per VC can be used in the place of a
simple elastic buffer.
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