Virtual-Channel Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 91

data
valid
ready

sender receiver

ready[0]
ready[1]
ready[2]

valid[0]
valid[1]
valid[2]

Fig. 6.2 Virtual channels require the addition of separate buffers for each VC at the receiver's
side and at the same time call for enhancements to the flow control signaling to accommodate the
multiple and independent flows travelling in each VC

once per packet. To support the multiple independent queues link-level flow control
is also augmented and includes separate information per virtual channel.
Ready/valid handshake on each network channel cannot distinguish between
different flows. This feature prevents the interleaving of packets and the isolation
of traffic flows, while it complicates deadlock prevention. A channel that supports
VCs consists of a set of data wires that transfer one flit per clock cycle, and as many
pairs of control wires valid(i )/ready(i ) as the number of VCs. Figure 6.2 shows an
example of a 3-VC elastic channel. Although multiple VCs may be active at the
sender, flits from only one VC can be sent per clock cycle; only one valid(i ) signal
is asserted per cycle. The selection of the flit that will traverse the link requires
some form or arbitration that will select one VC from those that hold valid flits. At
the same time, the receiver may be ready to accept flits that can potentially belong
to any VC. Therefore, there is no limitation on how many ready(j ) signals can be
asserted per cycle.
In VC flow control, both the buffering resources and the flow-control handshake
wires have been multiplied with the number of VCs. Therefore, the abstract flow
control model developed for the single-lane case in Chap. 2 should be enhanced to
support virtual channels. As shown in Fig. 6.3 a, we use a separate slot counter for
each VC that gets updated by the corresponding buffer and reflects via the ready
signal the status of the VC buffer. Normally, only one VC will drain a new flit
and thus the status of only one slot counter will be updated. Of course the case
of multiple VCs draining flits in parallel can be supported. Keeping the rate of
incoming flits equal to the rate of outgoing flits (leaving the receiver's buffer), it
is safe to assume that only one update will be asserted in each clock cycle.
Moving the slot counters at the sender side, as shown in Fig. 6.3 b transforms the
flow control mechanism to the equivalent credit-based flow control for VCs. The
i th VC is eligible to send a new flit as long as creditCount Œi > 0 meaning that
there is at least one empty slot at the downstream buffer for the i th VC. When a
new flit leaves the sender it decrements the corresponding credit counter, while the
credit updates returned per cycle are indexed by the corresponding credit update
wire (update[i ]).
Instead of transferring V valid signals and V credit update signals in the forward
and in the backward direction, it is preferable to encode the id of the valid VC and