SystemVerilog Simulation Semantics - SVA: The Power of Assertions in SystemVerilog - page 51

23 module top();
24 logic r, g;
25 logic clock = 1'b0;
26 always #5 clock <= !clock;
27 procReq dut(r, g, clock);
28 test tb(clock, r, g);
29 endmodule : top
Signal value changes ordered by regions until time 5 are shown in Table 3.1 . 2
See also Exercise 3.3 .
Table 3.1 Signal value changes (Example 3.7 )
Initialization
allow =X(Line 2 ), proceed =Z(Line 3 ),
req =X, gnt =X, clk =X(Line 1 )
r =X, g =X(Line 24 ), clock =0(Line 25 ),
sync =X, request =X, grant =X(Line 10 ), oldreq =0(Line 11 )
Time 0
Active region
clk =0(Line 1 ), proceed =X(Line 4 ), sync =0(Line 10 )
Reactive region
grant =0(Line 12 ), request =0(Line 14 )
Active region
gnt =0, req =0(Line 1 ), proceed =0(Line 4 )
Time 5
NBA region
clock =1(Line 26 ),
Active region
clk =1(Line 1 ), sync =1(Line 10 )
NBA region
allow =0(Line 5 )
Observed region
Assertion a1 evaluation. No failure detected (Line 7 )
Re-NBA region
oldreq =0(Line 17 ),
request =1(Line 18 , it is assumed that $random returns an odd number)
Active region
req =1(Line 1 )
Time 10
2 The LRM is ambiguous about net initialization: The default initialization value for a net shall be
the value Z . Our understanding is that in the beginning of simulation all nets are initialized with Z;
hence proceed initially assumes the value of Z. However, not all simulators implement the net
initialization this way.