SystemVerilog Simulation Semantics - SVA: The Power of Assertions in SystemVerilog - page 50

Fig. 3.2 Three main regions and sets

Simulation keeps running until there are no more events to execute.

Example 3.7. To explain how simulation is performed across these regions,
consider module procReq processing requests and program test generating stimuli
for it.

1 module procReq ( input logic req, gnt, clk);
2

logic allow;

wire proceed;

3

assign proceed = allow && gnt;

4

always @( posedge clk) allow <= req;

5

always @( posedge proceed) processData();

6

a1: assert property (@( posedge clk) req |=> proceed || !gnt);

7

endmodule : procReq

8

9
10 program test( input logic sync, output logic request, grant);
11 logic oldreq = 1'b0;
12 assign grant = oldreq;
13 initial begin
14 request = 1'b0;
15 for ( int i = 0; i < 50; i++) begin
16 @( posedge sync);
17 oldreq <= request;
18 request <= $random;
19 end
20 end
21 endprogram : test
22