Hardware Reference
In-Depth Information
Assume that the value of
b
changes from 1 to 0, and the value of
c
changes from
0 to 1. Since at the beginning of the simulation tick the values of
b
and
c
were
1 and 0, correspondingly, the value of
a
was 1. At the end of the simulation tick
(assuming no more value transitions for
b
and
c
), the values of
b
and
c
are 0 and
1, correspondingly, and therefore, the value of
a
remains 1. In the middle, however,
the situation may be different.
If both
b
and
c
change prior to evaluation of
a
or if
c
changes first, the value of
a
remains unchanged during the entire simulation tick. If the order of evaluation is
b
,
a
,
c
,
a
, then the first time
a
gets value of 0 and the second time it becomes 1 again.
In the latter case we have a glitch: though the initial and the final value of a is 1 in
this simulation tick, it is changed to 0 in the middle of the simulation tick.
t
If the RTL is not well-formed, the final result may depend on the evaluation order.
Such a situation is called a simulation
race
.
Example 3.6.
The following code is an example of a simulation race.
logic
clk,a,b;
...
always
@(
posedge
clk) a <= b;
Assume that both
b
and
clk
transition from 0 to 1. If the value of
b
changes
before
the change of
clk
,
a
will receive 1, the
new
value of
b
.Ifthevalueof
b
changes
after
the change of
clk
,
a
will retain 0, the
old
value of
b
. Thus the final
value of
a
depends on the actual order of the evaluation of events.
t
3.5
Region Sets
The regions Active, Inactive and NBA are all confined to the Active region set. The
execution iterates over the queues in a region set until all events scheduled in any
of its region queues are executed. Certain events, however, may be scheduled in the
other regions.
The processing of events is sequentially ordered into distinct regions, where each
region manages and executes events that are scheduled in the region. The processing
proceeds from one region to the next and can iterate until no further processing is
needed in any region for the given time step.
We discuss the role of the following regions and region sets. Other regions are
not important for the understanding of assertion semantics.
1. Preponed region
2. Active region set
3. Observed region
4. Reactive region set
5. Postponed region
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