SystemVerilog Simulation Semantics - SVA: The Power of Assertions in SystemVerilog - page 47

the register, its value is further propagated by the new update event entered in the
Active region queue. Algorithmically, the following steps are taken.

1. Execute events from the Active region queue. New events may be issued and
entered in the appropriate queues. Execute until all events are consumed.
2. Transfer events from the Inactive region queue to the Active region queue and
return to Step 1 . Skip this step if there are no events in the Inactive queue.
3. Execute events from the NBA region queue. New update events issued from this
execution are entered in the Active region queue. Return to Step 1 .

The above algorithm is iterated until there are no more events left in any queue
in the current time.

3.4 Determinism and Nondeterminism

As we saw in the previous section the order of event execution is not always
deterministic. The simulators normally will order the events in an optimal way to
avoid redundant computations, but one cannot rely on that. RTL should be well-
formed: the results of its simulation should be deterministic regardless of the actual
execution order of events.

Example 3.4. To illustrate the concept of determinism, consider the following
continuous assignments:

wire a, b, c, d;
...
assign a=b&c;
assign b=d;
Assume that nets c and d received new values. Then the continuous assignments
to a and b are scheduled for execution. The order of their execution is arbitrary.
If the assignment to a executes first, then it is scheduled for execution again after
execution of the assignment to b since its left-hand side depends on b . At the end of
the simulation step (assuming that the values of c and d do not change anymore)
a and b receive the same values regardless of the actual order of assignment
execution and update event processing. Normally, the simulators will first execute
the second assignment and then the first one to avoid redundant computations. t

The determinism does not guarantee the absence of glitches. A glitch is a
situation when a signal retains the same value at the end of the simulation tick
as it has at its beginning, but the value changes somewhere in the middle of the
simulation tick.

Example 3.5. The following code may result in a glitch in the signal a .
wire a, b, c;
...
assign a=b|c;