Checker Libraries - SVA: The Power of Assertions in SystemVerilog - page 554

24.4 Converting Module-Based Checkers to the New Format

The set of transformations include the following items:

￿ Replace 'define for various constants by typedef declarations using an enum
type whenever possible.
￿ Replace always with always_ff , always_comb or always_latch .
￿ Create compile-time checks on elaboration-time constant values.
￿ Use initial procedures only for indicating that the enclosed assertions should have
only one evaluation attempt. Initialize variables in their declaration.
￿ Change interface definition to include original parameters as regular arguments.
￿ Provide inference functions as default arguments to clock and reset.
￿ Provide default actual arguments wherever appropriate.
￿ Generalize the type of arguments to sequence or property wherever the checker
properties can admit such operands.
￿ Checker instance identification task calls in initial procedures should be replaced
by initial and an immediate assert statement on true, with a pass action statement
displaying the required identification message.
￿ Consider using covergroup statements to provide more detailed coverage,
selectable by an argument.
￿Add default clocking and disable iff declarations and simplify assertions.
￿ Place the new checkers in a package for easy and controlled access from a design
unit.

Exercises

24.1. Suppose that your design contains some legacy code with module -based
checker instances while new parts of the design should use a checker -based version
of the same checkers. The latter have the same names as the old module based
ones, but are enclosed in a package. How can you use both of these checkers but in
different parts of the design without name clashes?

24.2. The OVL checkers can be obtained from Accellera at [ 10 ]. Modify the OVL
SVA checker assert_proposition into the checker form. What kind of assertion
should it use, concurrent, immediate, or deferred?

24.3. When transforming the OVL assert_handshake checker into the checker
form, we omitted any discussion on x/z checking on the arguments req and ack .
This is because the actual arguments can be temporal sequences in which case
we cannot use $isunknown on the argument to check for the presence of x/z .
What would you provide as a solution to the user? Are any extensions to the
SystemVerilog language necessary?

24.4. List some extensions to the SystemVerilog language that would be useful to

have for creating effective checker libraries.