Checker Libraries - SVA: The Power of Assertions in SystemVerilog - page 553

a function that detects x/z in sequences and properties, or an enhancement in the
simulator to evaluate assertion in a pessimistic fashion.
The following is an example of instantiation of the new checker. For simplicity,
all elaboration-time arguments take on default values.

Example 24.10. assert_handshake checker instantiation
module m;
bit clk;
logic rst_n, request,
acknowledgment, endtrans;

default clocking @( posedge clk iff enabled);
endclocking

default disable iff rst_n;

//... some design code ...

always @( posedge clk) begin
assert_handshake chk_handshake_inst(
.req($rose(request)),
.ack(acknowledgment ##1 endtrans));
if (!rst_n) begin
//... some design procedure ...
end
end

//... some design code ...

t

endmodule

The main points are:

￿ The checker instantiation syntax is similar to that of a module, except that there
is no parameter section.
￿ It can be instantiated in an always procedure.
￿The reset argument is inferred from default disable declaration.
￿ The clocking event is inferred from the always procedure, hence even though
default clocking is defined, the clock from the always procedure takes
precedence.
￿ The actual argument for the formal argument req is $rose(request) ; its clock
is obtained from the default clocking defined in the module.
￿ The actual argument for ack is a sequence expression.
In the next and final section, we summarize the transformations to consider
when converting the old-style module-based checkers into the new format based
on checker encapsulation. This may be of interest when it is not desired to support
two different formats of a checker library.