Checker Libraries - SVA: The Power of Assertions in SystemVerilog - page 547

end : COVER_L2
'endif

endchecker : onehot0

t

This combinational checker illustrates many of the features that the checker
encapsulation provides over the simpler let -based form:
￿ Coverage can be enabled globally for all checker instances by defining the symbol
COVER_ON . Similarly, verification statements ( assert or assume ) can be globally
enabled by defining ASSERT_ON .
￿ Synthesizable form is selected by a conditional generate block controlled by
the argument synthesis that has as default actual value the macro symbol
SYNTHESIS . This allows overriding the global selection if so required.
￿ The reset condition may be inferred from a default disable iff declaration.
￿ Deferred assert ( usage_kind == ASSERT )or assume
( usage_kind == ASSUME ) statement or none can be selected using the argument
usage_kind .
￿ When an invalid value is provided for cover_level , no coverage is enabled in
this instance and an error message is issued.
￿ When an invalid value (or NONE ) is provided for usage_kind , no verification
statement ( assert or assume ) is enabled in this instance and a warning message
is issued.
￿For Cover_onehot0_2 , we use deferred #0 because final cannot be used when
a user defined function or task is invoked in the action block. Otherwise, final
would have been preferred.
￿ Two levels of functional coverage are provided, they can be individually enabled
or disabled:

- Level 1—when cover_level == 1 is selected, it collects information on how
many times a one hot or 0 condition was encountered while not disabled by
reset.
- Level 2—when cover_level == 2 is selected, the covergroup classifies the
bit positions that are set to 1 when the one hot condition holds. A deferred
cover statement is used to trigger sampling of the bit position index by calling
the sample method of the covergroup in the pass action statement of the
deferred cover statement.
- Both levels can be selected by setting
cover_level == 3 .

The checker can be instantiated in a simpler way than the one using a let
declaration because the disable condition can be inferred:

Example 24.5. Combinational checker instantiation
'define ASSERT_ON
module m( input logic [3:0] r1,
output logic [3:0] r2,
input logic rst_n);