Checker Libraries - SVA: The Power of Assertions in SystemVerilog - page 546

"\nonly 1(level 0), 2(level 2), 3(both)",
"or 0 (disabled) are allowed");
if (usage_kind != ASSERT || usage_kind != ASSUME)
$warning("No assert or assume selected");
if (synthesis) begin : SYNTH
let check_onehot0 (sig, reset) =
((!|reset_n) || $onehot0(sig));
let cover_onehot0 (sig, reset) =
((|reset) && $onehot0(sig));
end : SYNTH
else begin : NO_SYNTH
let check_onehot0 (sig, reset) =
((|reset === 0) || $onehot0(sig) && !$isunknown(reset));
let cover_onehot0 (sig, reset) =
((|reset === 1) && $onehot0(sig));
end : NO_SYNTH
'ifdef ASSERT_ON
if (usage_kind == ASSERT) begin : ASSERT
Assert_onehot0:
assert final (check_onehot0(sig, reset))
else $error(msg);
end : ASSERT
else if (usage_kind == ASSUME) begin : ASSUME
Assume_onehot0:
assume final (check_onehot0(sig, reset))
else $error(msg);
end : ASSUME
'endif
'ifdef COVER_ON
if (cover_level & 1) begin : COVER_L1
Cover_onehot0_1:
cover final (cover_onehot0(sig, reset));
end : COVER_L1
if (!synthesis && (cover_level & 2))
begin : COVER_L2
function int position( logic $bits(sig) arg);
for ( int i = 0; i < $bits(sig); i++)
if (sig[i] === 1) return i;
return 0;
endfunction // position
covergroup cg_onehot0_2 with
function sample( int index);
coverpoint index;
endgroup
cg_onehot0_2 onehot0_2_index = new ();
Cover_onehot0_2:
cover #0 (cover_onehot0(sig, reset))
onehot0_2_index.sample(position(sig));